Cadence Virtuoso Data Path Design

I led a team of three engineers focused on designing a fully functional 8-bit microprocessor data path in both the schematic and layout views of Cadence Virtuoso. Winning third place, the project used CMOS circuitry and design conventions to implement SRAM, ALU, and Shifter blocks. I was personally responsible for the entire schematic and layout design of the SRAM block, reducing its total area and ensuring the functionality of two read ports and one write port. I also troubleshot and reviewed the ALU and Shifter blocks, designed all inter-block connections, and spearheaded proposals, reports, and presentations. All stages of the data path were designed from scratch and were tested to ensure proper functionality, minimum time delay, and negligible voltage drop.