Verilog/VHDL Design

I have completed multiple projects designing FPGA logic circuits in Verilog and VHDL, using the Xilinx Vivado design suite. Most notably, I have used basic logic gates to build more complex structures, like multiplexers, flip-flops, and registers. I then used instances of these more complex units to build two separate ALU designs, one 4-bit and one 8-bit. The blocks were capable of accurately calculating addition, subtraction, increment, and decrement of two inputs, as well as AND, OR, XOR, XNOR Boolean logic operations. The ALU could also pass or invert either input. The results of both ALU designs was simulated and verified using force command codes in the Xilinix Vivado FPGA simulation environment.